1. Field of the Invention
The present invention relates to a technique of generating a clock signal synchronized with a transition of a received data signal, and more particularly to a clock data recovery (also called CDR hereinafter) circuit capable of generating a clock signal synchronized with a data signal even when the frequency of a clock (Recovered CLOCK) signal synchronized with the data signal is different from the frequency of a clock (CLOCK) signal used in a semiconductor integrated circuit.
2. Description of the Background Art
In recent years, an interface circuit for transmission of serial data, such as PCI (Peripheral Component Interconnection)-Express or Serial-ATA (AT Attachment) is used in communication equipment and computers. A conventional technique using a CDR circuit as such an interface circuit includes “A 50-mW/ch 2.5-Gb/s/ch Data Recovery Circuit for the SFI-5 Interface Using Novel Eye-tracking Method”, 2003 Symposium on VLSI Circuits Digest of Technical Papers, pp. 57-60.
This document discloses a CDR circuit formed of a data edge detector, an up/down decision circuit, a one-period clock phase pointer, an eight-phase clock divider, a selector selecting one from eight phase clocks, and the like and using internal clocks having phase differences of 0° and 90°.
In the prior art as described above, in order to generate precise eight phase clocks by the eight-phase clock divider, the two phase internals clock input to the CDR circuit are required to have precise phase differences of 0° and 90°. Therefore, there need to be provided outside the CDR circuit a circuit generating two phase internal clocks and a clock distribution circuit performing phase control between two phases, thereby complicating the circuit configuration.
In addition, in order to precisely synchronize the clock signal with the transition of the data signal, the division number of one period needs to be made larger than eight, which increases the number of eight-phase clock dividers. Since an eight-phase clock divider is an analog circuit having a through current path, the current consumption in the CDR circuit is increased.
Furthermore, since the selector receives an output from the one-period clock phase pointer to select one from eight phase input clocks, a narrow-width pulse signal such as glitch noise or hazard may sometimes be output in switching of a propagation path, resulting in a malfunction of the system.